1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the contact level of a semiconductor device, in which contact areas of semiconductor circuit elements, such as gate electrodes and drain and source regions, are connected to the metallization system of the semiconductor device on the basis of contact elements.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, a large number of field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain terminal and a source terminal.
On the basis of the field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, memory devices and the like. Due to the reduced dimensions, the operating speed of the circuit components has been increased with every new device generation, wherein, however, the limiting factor of the finally achieved operating speed of complex integrated circuits is no longer the individual transistor elements but the electrical performance of the complex wiring network, which may be formed above the device level including the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as vias. These interconnect structures comprise an appropriate metal and provide the electrical connection of the individual circuit elements and of the various stacked metallization layers.
Furthermore, to establish a connection of the circuit elements with the metallization layers, an appropriate contact structure is provided, which connects to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and to a respective metal line in the first metallization layer. The contact structure may comprise contact elements or contact plugs formed in an interlayer dielectric material that encloses and passivates the circuit elements. Upon further shrinkage of the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability and performance of the integrated circuits. Consequently, in lower lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required packing density in accordance with the density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level may have to be provided with appropriate critical dimensions on the same order of magnitude. The contact elements may typically represent plugs, trenches and the like which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically, the interlayer dielectric material is formed first and is then patterned so as to receive contact openings, which may extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. For this purpose, openings of very different depth may have to be formed in the interlayer dielectric material in order to connect to gate electrode structures or any other conductive lines formed above the semiconductor layer, while other contact openings have to extend down to the semiconductor layer, i.e., any contact areas formed therein. In particular, in densely packed device regions, the lateral size of the drain and source areas, and thus the available area for the contact regions, may be 100 nm and less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy, while the difference in etch depth may additionally contribute to the overall complexity of the patterning process. After exposing the contact areas, frequently provided in the form of metal silicide regions, a barrier material is frequently provided, for instance in the form of a material system including titanium and titanium nitride, wherein the titanium material may provide the required adhesion characteristics, while the titanium nitride material may preserve integrity of the interlayer dielectric material during the subsequent deposition of the tungsten material, which may be accomplished on the basis of sophisticated chemical vapor deposition (CVD) techniques in which a direct contact between silicon dioxide based materials and the deposition ambient for depositing the tungsten material is to be avoided. Typically, the actual deposition of the tungsten material may be preceded by the deposition of a nucleation layer based on tungsten, which may be accomplished by a dedicated deposition step, after which the actual fill material may be provided. After the deposition of these materials, any excess material may be removed, for instance by chemical mechanical polishing (CMP), thereby forming the isolated contact elements in the interlayer dielectric material. Although the process sequence for patterning the contact openings and filling these openings with barrier materials and tungsten results in contact elements having a desired contact resistivity for semiconductor devices with critical dimensions of 50 nm, a further reduction of the size of the transistors may result in an increased contact resistivity, which may no longer be compatible with the device requirements. That is, upon further device scaling, the increased contact resistivity, which may result from conventional tungsten-based contact regimes, may represent a limiting factor of the operating speed of the integrated circuits, thereby at least partially offsetting many advantages obtained by the further reduction of the critical dimensions in the device level.
In particular, the material removal process for removing any excess material of the tungsten after filling the contact openings may represent a critical process step, since a reliable removal of any excess metal has to be guaranteed, thereby requiring appropriately set over-polishing process time, which, however, may result in a pronounced surface topography. Consequently, the further processing, i.e., the deposition and patterning of the dielectric material of the first metallization layer, may have to be adapted to the pronounced surface topography. Furthermore, in particular, increased contact resistivity has been identified to be caused by the inferior resistivity of the conductive barrier materials, since, upon further device scaling, the amount of tungsten material may have to be reduced, while the thickness of the conductive barrier material may not be arbitrarily reduced in the same manner. Consequently, the fraction of the overall contact resistance of the conductive barrier material increases upon further device scaling. Moreover, the discontinuity in the materials between the first metallization layer and the contact elements, i.e., the transition from the highly conductive copper to the tungsten material in combination with the conductive barrier material formed in the metal line may increasingly contribute to the overall contact resistivity, in particular upon further device scaling. Consequently, in sophisticated semiconductor devices, the conventional tungsten-based contact regime may increasingly reduce device performance, even if highly sophisticated semiconductor contact elements may be provided in the device level of the semiconductor device.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.